4. Examples¶
4.1. A Simple VHDL Template¶
4.1.1. Register Description File¶
Registers:
entries:
- ref: Channel
number: 8
offset: 0x0000
- ref: Egroup
number: 7
offset: 0x1000
- ref: GBT
number: 24
offset: 0x2000
Channel:
type: W
default: 0
entries:
- name: Dir
desc: null
bitfield:
- range: 0
- name: ChWidth
desc: '2,4,8,16,or 112, 120 bits'
bitfield:
- range: 6..0
- name: ChStart
desc: first bit of the channel in the GBT word
bitfield:
- range: 6..0
- name: Ewidth
desc: width of the E-link comprising the channel
bitfield:
- range: 3..0
- name: hasStreams
desc: null
bitfield:
- range: 0
- name: hasChnkLen
desc: null
bitfield:
- range: 0
- name: MaxChnkLen
desc: null
bitfield:
- range: 15..0
- name: hasChkSum
desc: "a 16-bit 1's-complement checksum is at the end of the packet"
bitfield:
- range: 0
- name: FromSCA
desc: Decode HDLC
bitfield:
- range: 0
- name: DOLL
desc: Direct Output Low Latency Link
bitfield:
- range: 0
- name: Busy
desc: BUSY commands may be sent on this channel
bitfield:
- range: 0
- name: TTCin
desc: source of raw TTC infor
bitfield:
- range: 0
- name: chk8b10b
desc: use commas and check 8b/10b encoding is valid
bitfield:
- range: 0
- name: dec8b10
desc: forward decoded 8b/10 data
bitfield:
- range: 0
- name: SOPEOP
desc: Start-of-Packet and End-of-Packet symbols define packet boundaries
bitfield:
- range: 0
- name: ToSCA
desc: encode HDLC
bitfield:
- range: 0
- name: TTCopt
desc: 'if >0, destination of TTC info: 0, 2 (A&B ch), 4, 8 bits'
bitfield:
- range: 1..0
- name: DILL
desc: Direct Input Low Latency Link
bitfield:
- range: 0
- name: TDAT
desc: destination for scheduled data transfers
bitfield:
- range: 0
Egroup:
type: W
default: 0
entries:
- name: EprocEnable
desc: Enables for the E-procs in the group
bitfield:
- range: 14..0
- name: EclockRate
desc: 40,80,160, 320, (640)
bitfield:
- range: 2..0
GBT:
entries:
- name: gbt_format
desc: Wide or Normal
bitfield:
- range: 0
type: W
default: 0
4.1.2. Template File¶
-- WUPPER: VHDL configuration code
{% for group in tree|list_nodes_recursively if group.is_sequence and group.index == 0 and group.name != 'Registers' %}
-----------------------------------------------------
-- {{group.full_name}} record definition
-----------------------------------------------------
--
type {{group.full_name}} is
record
--
-- {{group.full_name}} attributes
--
{% for register in group.nodes %}
{{"%-30s"|format(register.full_name)}} : {{"%-32s"|format(register|vhdl_logic_vector|semi}} {{register.desc|vhdl_comment()}}
{% endfor %}
end record
-----------------------------------------------------
-- array of {{group.full_name}}s in {{group.parent.full_name}}
-----------------------------------------------------
--
type {{group.full_name}}_array is array (0 to {{group.parent.nodes|count-1}}) of {{group.full_name}};
{% endfor %}
4.1.3. Output File¶
-- WUPPER: VHDL configuration code
-----------------------------------------------------
-- Channel record definition
-----------------------------------------------------
--
type Channel is
record
--
-- Channel attributes
--
Dir : std_logic_vector(0 downto 0);
ChWidth : std_logic_vector(6 downto 0); -- 2,4,8,16,or 112, 120 bits
ChStart : std_logic_vector(6 downto 0); -- first bit of the channel in the GBT word
Ewidth : std_logic_vector(3 downto 0); -- width of the E-link comprising the channel
hasStreams : std_logic_vector(0 downto 0);
hasChnkLen : std_logic_vector(0 downto 0);
MaxChnkLen : std_logic_vector(15 downto 0);
hasChkSum : std_logic_vector(0 downto 0); -- a 16-bit 1's-complement checksum is at the end of the packet
FromSCA : std_logic_vector(0 downto 0); -- Decode HDLC
DOLL : std_logic_vector(0 downto 0); -- Direct Output Low Latency Link
Busy : std_logic_vector(0 downto 0); -- BUSY commands may be sent on this channel
TTCin : std_logic_vector(0 downto 0); -- source of raw TTC infor
chk8b10b : std_logic_vector(0 downto 0); -- use commas and check 8b/10b encoding is valid
dec8b10 : std_logic_vector(0 downto 0); -- forward decoded 8b/10 data
SOPEOP : std_logic_vector(0 downto 0); -- Start-of-Packet and End-of-Packet symbols define packet boundaries
ToSCA : std_logic_vector(0 downto 0); -- encode HDLC
TTCopt : std_logic_vector(1 downto 0); -- if >0, destination of TTC info: 0, 2 (A&B ch), 4, 8 bits
DILL : std_logic_vector(0 downto 0); -- Direct Input Low Latency Link
TDAT : std_logic_vector(0 downto 0); -- destination for scheduled data transfers
end record
-----------------------------------------------------
-- array of Channels in Registers
-----------------------------------------------------
--
type Channel_array is array (0 to 38) of Channel;
-----------------------------------------------------
-- Egroup record definition
-----------------------------------------------------
--
type Egroup is
record
--
-- Egroup attributes
--
EprocEnable : std_logic_vector(14 downto 0); -- Enables for the E-procs in the group
EclockRate : std_logic_vector(2 downto 0); -- 40,80,160, 320, (640)
end record
-----------------------------------------------------
-- array of Egroups in Registers
-----------------------------------------------------
--
type Egroup_array is array (0 to 38) of Egroup;
-----------------------------------------------------
-- GBT record definition
-----------------------------------------------------
--
type GBT is
record
--
-- GBT attributes
--
gbt_format : std_logic_vector(0 downto 0); -- Wide or Normal
end record
-----------------------------------------------------
-- array of GBTs in Registers
-----------------------------------------------------
--
type GBT_array is array (0 to 38) of GBT;
4.2. A List of all Registers¶
4.2.1. Register Description File¶
Registers:
default: 0
type: W
entries:
- ref: Channel
number: 2
offset: 0x0000
- ref: GBT
number: 4
offset: 0x1000
Channel:
entries:
- name: hasChkSum_{index}
desc: a 16-bit 1’s-complement checksum is at the end of the packet
bitfield:
- range: 15..0
- name: TDAT_{index}
desc: destination for scheduled data transfers
bitfield:
- range: 0
GBT:
entries:
- name: gbt_format_{index}
desc: Wide or Normal
bitfield:
- range: 0
4.2.2. Template File¶
All Registers:
{% for item in nodes['Registers']|list_nodes_recursively %}
{% if item.is_register %}
{{ "%-34s"|format(item.full_name) }} @ {{ item.address|hex}} ({{ item.offset|hex}})
{% endif %}
{% endfor %}
4.2.3. Output File¶
All Registers:
hasChkSum_0 @ 0x0000 (0x0000)
TDAT_0 @ 0x0010 (0x0000)
hasChkSum_1 @ 0x0020 (0x0000)
TDAT_1 @ 0x0030 (0x0000)
gbt_format_0 @ 0x1000 (0x0000)
gbt_format_1 @ 0x1010 (0x0000)
gbt_format_2 @ 0x1020 (0x0000)
gbt_format_3 @ 0x1030 (0x0000)