BinPy.Sequential package

Submodules

BinPy.Sequential.counters module

class BinPy.Sequential.counters.BinaryCounter(bits, clk, data=0, preset=1, clear=1)

Bases: BinPy.Sequential.counters.Counter

An N-Bit Binary Counter Output connectors can be referenced by –> BinaryCounter_instance_name.out

>>> From BinPy import *
>>> clock = Clock(0, 100)  #A clock with leading edge = 0 and frequency = 100Hz
>>> clock.start()
>>> clk_conn = clock.A
>>> b = BinaryCounter(2, clk_conn)
>>> for i in range(0, 5):
>>>     b.trigger()
>>>     print(b.state)
[0, 1]
[1, 0]
[1, 1]
[0, 0]
[0, 1]

class BinPy.Sequential.counters.Counter(bits, clock_connector, data, preset, clear)

Bases: object

Base class for all counters

disable()

enable()

resetCounter()

setCounter()

setInput(t, enable)

state()

trigger(ffnumber=None)

class BinPy.Sequential.counters.DecadeCounter(clock_connector, data=0, preset=1, clear=1)

Bases: BinPy.Sequential.counters.Counter

A 4-Bit Decade Counter

class BinPy.Sequential.counters.JohnsonCounter(bits, clock_connector, preset=1, clear=1)

Bases: BinPy.Sequential.counters.Counter

An N-bit Johnson Counter

reset()

set()

state()

trigger()

class BinPy.Sequential.counters.NBitDownCounter(bits, clock_connector, data=0, preset=1, clear=1)

Bases: BinPy.Sequential.counters.Counter

An N-Bit Down Counter

>>> From BinPy import *
>>> clock = Clock(0, 100)  #A clock with leading edge = 0 and frequency = 100Hz
>>> clock.start()
>>> clk_conn = clock.A
>>> counter = NBitDownCounter(4, clk_conn)
>>> for i in range(0, 8):
>>>     counter.trigger()
>>>     print(counter.state)
[1, 1, 1, 1]
[1, 1, 1, 0]
[1, 1, 0, 1]
[1, 1, 0, 0]
[1, 0, 1, 1]
[1, 0, 1, 0]
[1, 0, 0, 1]
[1, 0, 0, 0]
[0, 1, 1, 1]
[0, 1, 1, 0]
[0, 1, 0, 1]
[0, 1, 0, 0]
[0, 0, 1, 1]
[0, 0, 1, 0]
[0, 0, 0, 1]
[0, 0, 0, 0]
[1, 1, 1, 1]

class BinPy.Sequential.counters.NBitRippleCounter(bits, clock_connector, data=0, preset=1, clear=1)

Bases: BinPy.Sequential.counters.Counter

An N-Bit Ripple Counter

>>> From BinPy import *
>>> clock = Clock(0, 100)  #A clock with leading edge = 0 and frequency = 100Hz
>>> clock.start()
>>> clk_conn = clock.A
>>> counter = NBitRippleCounter(4, clk_conn)
>>> for i in range(0, 8):
>>>     counter.trigger()
>>>     print(counter.state)
[0, 0, 0, 1]
[0, 0, 1, 0]
[0, 0, 1, 1]
[0, 1, 0, 0]
[0, 1, 0, 1]
[0, 1, 1, 0]
[0, 1, 1, 1]
[1, 0, 0, 0]
[1, 0, 0, 1]
[1, 0, 1, 0]
[1, 0, 1, 1]
[1, 1, 0, 0]
[1, 1, 0, 1]
[1, 1, 1, 0]
[1, 1, 1, 1]
[0, 0, 0, 0]

class BinPy.Sequential.counters.OctalCounter(clock_connector, data=0, preset=1, clear=1)

Bases: BinPy.Sequential.counters.Counter

A 4-Bit Octal Counter

class BinPy.Sequential.counters.RingCounter(bits, clock_connector, preset=1, clear=1)

Bases: BinPy.Sequential.counters.Counter

An N-bit Ring Counter

reset()

set()

state()

trigger()

class BinPy.Sequential.counters.Stage14Counter(clock_connector, data=0, preset=1, clear=1)

Bases: BinPy.Sequential.counters.Counter

A 14-Bit Counter

BinPy.Sequential.registers module

class BinPy.Sequential.registers.FourBitLoadRegister(A0, A1, A2, A3, clock, clear, load)

Bases: BinPy.Sequential.registers.Register

Four Bit Register with Load Inputs: A0, A1, A2, A3 Clock: clock Clear: clear Load: load Methods: setLoad()

Example:

>>> from BinPy import *
>>> c = Clock(1, 500)
>>> c.start()
>>> fr = FourBitLoadRegister(1, 0, 1, 1, c, 1, 1)
>>> fr.output()
[1, 0, 1, 0]

setLoad(load)

trigger()

class BinPy.Sequential.registers.FourBitRegister(A0, A1, A2, A3, clock, clear)

Bases: BinPy.Sequential.registers.Register

Four Bit Register Inputs: A0, A1, A2, A3 Clock: clock Clear: clear

Example:

>>> from BinPy import *
>>> c = Clock(1, 500)
>>> c.start()
>>> fr = FourBitRegister(1, 0, 1, 1, c, 1)
>>> fr.output()
[1, 0, 1, 1]

trigger()

class BinPy.Sequential.registers.Register(inputs, clock, clear)

Bases: object

Base class for all registers

getInputStates()

output()

setClear(clr)

setClock(clk)

setInput(index, value)

setInputs(*inputs)

setOutput(index, value)

class BinPy.Sequential.registers.ShiftRegister(inputs, clock, clear=1, circular=0)

Bases: BinPy.Sequential.registers.Register

Shift Register Inputs: [A0, A1, A2, A3] Clock: clock

Example:

>>> from BinPy import *
>>> c = Clock(1, 500)
>>> c.start()
>>> fr = ShiftRegister([1, 0, 0, 0], c)
>>> fr.output()
[1, 1, 0, 0]
>>> fr.output()
[1, 1, 1, 0]
>>> fr.output()
[1, 1, 1, 1]

trigger()

BinPy.Sequential.sequential module

class BinPy.Sequential.sequential.DFlipFlop(D, enable, clk, preset=1, clear=1, a=0, b=0)

Bases: BinPy.Sequential.sequential.FlipFlop

DATA Flip Flop ( Negative edge triggered )

D is the primary input. enable activates the Flip Flop. ( Negative edge triggered ) Clock triggers the output

Outputs are a ( q ) and b ( ~q )

setInputs(**inputs)

Sets the input connectors of DFlipFlop. Give input parameters as a dictionary

Ex.: dff.setInputs(D = dconnector, enable = enable_connector) Ex.2: dff.setInputs(enable = foo)

Usage of **inputs is to pass parameters as dict to to support partial change in input [ D or enable alone ]

Note: 1) When inputs are given as type-int - The D state alone is changed. The connections remain intact. 2) Setting the inputs does not trigger the Latch. Use trigger separately to trigger any change.

setOutputs(**outputs)

state()

Returns the current state of the DFlipflop

trigger()

class BinPy.Sequential.sequential.FlipFlop(enable, clk, a, b)

Super Class for all FlipFlops

Disable()

Enable()

resetff()

setff()

class BinPy.Sequential.sequential.JKFlipFlop(J, K, enable, clk, preset=1, clear=1, a=0, b=1)

Bases: BinPy.Sequential.sequential.FlipFlop

J K Flip Flop - Negative edge triggered

J and K are the two primary inputs. They are enabled by the third input enable. Clock triggers the Flip flop.

Outputs are a ( q ) and b ( ~q )

To Use : Set the inputs of JKFlipFlop and to trigger any change in input use trigger() method. call to the JKFlipFlop instance also triggers it and returns the current state as a list

setInputs(**inputs)

Sets the input connectors of Jk Flip flop. Give input parameters as a dictionary

Ex.: jk1.setInputs(J = J, K = K) Ex.2: jk2.setInputs(enable = foo)

Where J, K, foo are all Connector class instances.

This is done to support partial change in input [ only J or K etc ]

Note: 1) When inputs are given as type-int - The J and K states alone are changed. The connections remain intact. 2) Setting the inputs does not trigger the Latch. Use trigger separately to trigger any change.

setOutputs(**outputs)

state()

trigger()

Trigger will update the output when any of the inputs change.

class BinPy.Sequential.sequential.SRLatch(S, R, enable, clk, preset=1, clear=1, a=0, b=1)

Bases: BinPy.Sequential.sequential.FlipFlop

S and R are the two primary inputs. They are enabled by the third input enable. Clock is used to trigger the Latch.

Outputs are a ( q ) and b ( ~q )

To Use : Set the inputs of SRLatch and to trigger any change in input use trigger() method.

setInputs(**inputs)

Sets the input connectors of SRLatch. Give input parameters as a dictionary

Ex.: sr1.setInputs(S = S, R = R) Ex.2: sr2.setInputs(enable = en1)

[ where S, R, foo are all Connector class instances. ]

This is done to support partial change in input [ only S or R etc ]

Note: 1) When inputs are given as type-int - The S and R states alone are changed. The connections remain intact. 2) Setting the inputs does not trigger the Latch. Use trigger separately to trigger any change.

setOutputs(**outputs)

state()

Returns the current state of the SRLatch

trigger()

class BinPy.Sequential.sequential.TFlipFlop(T, enable, clk, preset=1, clear=1, a=None, b=None)

Bases: BinPy.Sequential.sequential.JKFlipFlop

Toggle Flip Flop. Negative edge triggered.

Inputs are T and enable. Clock triggers the circuit

Outputs are: a = ( q ) b = ( q~ )

setOutputs(**outputs)

state()

trigger()

Module contents