vtb

decida.vtb.vtb(netlistdir, testbench, check=False, mod_dir=None)

synopsis:

Extract verilog testbench files from Cadence NCsim netlister.

arguments:

netlistdir (str)

directory where netlists have been produced

testbench (str)

testbench name

check (bool, default=False)

if True, produce check files for debugging (NOT USED)

mod_dir (str, default=None)

directory to place modified modules